
- 14 -
1
2
3
4
-
+
5
6
7
8
-
+
CH1
CPU
13
14
9
10
11
12
-
+
-
+
-
+
CH2
input
circuit
CH1
input
circuit
Insulation
circuit
Insulation
circuit
Insulation
circuit
Insulation
circuit
Display/Setting
key circuit
Power
circuit
CH1
output
circuit
CH2
output
circuit
Power supply
CH1 A1 output
CH2 A1 output
CH1
A2
output
CH1
A3
output
CH2
A2
output
CH2
A3
output
CH2
TC
TC
1
2
3
4
A
B
B
5
6
7
8
A
B
B
CPU
13
14
9
10
11
12
-
+
-
+
-
+
Power supply
Power
circuit
CH1
output
circuit
CH2
output
circuit
Insulation
circuit
Insulation
circuit
CH2
input
circuit
CH1
input
circuit
Display/Setting
key circuit
CH1
A2
output
CH1
A3
output
CH2
A2
output
CH2
A3
output
CH2 A1 output
CH1 A1 output
Insulation
circuit
Insulation
circuit
CH2
CH1
RTD
RTD
4.2 Terminal Arrangement and Circuit Configuration
SE2EA
(Fig. 4.2-1)
SE2RA
(Fig. 4.2-2)
Komentarze do niniejszej Instrukcji